Seam removal in high aspect ratio gap-fill
US12142480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Sep 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6831
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.