Transistor gate structures and methods of forming the same
US12142655B2 · kind B2 · utility
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18References
20Claims
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Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | May 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.