Current leakage management controller for reading from memory cells
US12148464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Mar 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.