Early detection of programming failure for non-volatile memory
US12148489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.