Memory cell in wafer backside
US12148682B2 · kind B2 · utility
1Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jun 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5286
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.