Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses
US12153524B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 30, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Sep 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.