Memory device and operation method thereof
US12154616B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Oct 24, 2023 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Oct 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.