Non-volatile memory with tuning of erase process
US12154630B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jun 3, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.