SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
US12159689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Feb 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.