Power semiconductor device with reduced strain
US12159909B2 · kind B2 · utility
0Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Nov 8, 2023 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.