Concurrent command limiter for a memory system
US12164811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2023 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Dec 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.