Method for resetting an array of resistive memory cells
US12165706B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 1, 2020 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Apr 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N−1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j−1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j−1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.