Molded silicon on passive package
US12165956B2 · kind B2 · utility
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15References
15Claims
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Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jan 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/552
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.