Substrate-less electrostatic discharge (ESD) integrated circuit structures

US12166031B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Biswajeet Guha · Hillsboro, US
• Brian J. Greene · Wappingers Falls, US
• Daniel Schulman · Hillsboro, US
• William Hsu · Hillsboro, US
• Chung-Hsun Lin · White Plains, US
• Curtis Tsai · Beaverton, US
• Kevin J. Fischer · Hillsboro, US

Key dates

• Filing date: Dec 22, 2020
• Grant date: Dec 10, 2024
• Expiry date: Mar 24, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.