High voltage device with linearizing field plate configuration
US12166476B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Dec 14, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jan 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.