Memory device including multiple decks of memory cells and pillars extending through the decks
US12167599B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 19, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.