Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation
US12169459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2023 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous processing system and method including a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to directly access the second memory using the mapped physical addresses according to memory extension operation. The first processor may be a reconfigurable processor, a reconfigurable dataflow unit, or a compute engine. The first processor may directly read data from or directly write data to the second memory while executing an application. The method may include configuring the first processor to directly access the second memory while executing an application for reading or writing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.