Three-dimensional memory devices and methods for forming the same
US12170257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2021 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Feb 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.