Dual contact process with stacked metal layers

US12170319B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin T. Cook · Berkeley, US
• Anand S. Murthy · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Nazila Haratipour · Hillsboro, US
• Ralph T. Troeger · Portland, US
• Christopher J. Jezewski · Portland, US
• I-Cheng Tung · Hillsboro, US

Key dates

• Filing date: Sep 25, 2020
• Grant date: Dec 17, 2024
• Expiry date: Apr 17, 2043

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.