Microelectronic devices, and related memory devices and electronic systems
US12171096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Jan 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.