Static random access memory with a supplementary driver circuit and method of controlling the same
US12176026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jun 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.