Patent · US Active

Semiconductor package with wettable flank

US12176272B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

Hui Min LER · Seremban, MY
Soon Wei WANG · Seremban, MY
Chee Hiong CHEW · Seremban, MY

Key dates

Filing date	Nov 17, 2022
Grant date	Dec 24, 2024
Priority date	—
Expiry date	Jan 28, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.