Memory devices having vertical transistors and methods for forming the same
US12176310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the first bonding interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.