Semiconductor package
US12176313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.