Localized spacer for nanowire transistors and methods of fabrication

US12176408B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sudipto Naskar · Portland, US
• Willy Rachmady · Beaverton, US
• Hsin-Fen Li · Hillsboro, US
• Christopher Parker · Medina, US
• Prashant Wadhwa · Portland, US
• Tahir Ghani · Portland, US
• Mohammad HASAN · Beaverton, US
• Jianqiang Lin · Cambridge, US

Key dates

• Filing date: Dec 22, 2020
• Grant date: Dec 24, 2024
• Expiry date: Feb 5, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.