Method for forming memory and memory
US12178036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.