Data representation for dynamic precision in neural network cores
US12182687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.