Memory array structures and methods of forming memory array structures
US12183396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.