Memory arrays and methods used in forming a memory array comprising strings of memory cells

US12185545B2 · kind B2 · utility

Inventors

• Collin Howder · Boise, US
• Chet E. Carter · Boise, US

Key dates

• Filing date: Jun 22, 2023
• Grant date: Dec 31, 2024
• Expiry date: Jun 22, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.