Bit error management in memory devices
US12189949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.