Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween

US12191354B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Manuj Nahar · Boise, US
• Vassil Antonov · Boise, US
• Kamal M. Karda · Boise, US
• Michael Mutch · Chardon, US
• Hung-Wei Liu · Jinshanmian, TW
• Jeffery B. Hull · Boise, US

Key dates

• Filing date: Jul 8, 2022
• Grant date: Jan 7, 2025
• Expiry date: Jul 8, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02532
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.