Semiconductor device with tunable channel layer usage and methods of fabrication thereof
US12191370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and being alternatingly disposed in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess, and forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. The insulation layer is above the base epitaxial layer and above a bottommost channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.