Wafer manufacturing method and laminated device chip manufacturing method
US12198990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Apr 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.