System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
US12204833B2 · kind B2 · utility
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Key dates
| Filing date | Sep 5, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Sep 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.