Routing instruction results to a register block of a subdivided register file based on register block utilization rate
US12204902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2021 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, processor, programming product and/or method for assigning instructions to destination register file blocks, and/or routing instructions, includes: providing a processing pipeline having two or more execution units configured to process instructions; providing a register file having register file entries configured to hold data, where the register file is subdivided into a plurality of register blocks and each register block has two or more register file entries; calculating a utilization rate for one or more register blocks; and assigning and/or routing an instruction to write its results to a register block based upon the utilization rate for that register block. Preferably the execution unit is configured to write its results to a single specific destination (rename) register block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.