Memory module with improved timing adaptivity of sensing amplification
US12205635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2023 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Aug 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.