Programming techniques to reduce programming stress in a memory device
US12205647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Aug 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the control gate of the selected word line from the first voltage to a programming voltage over a first duration. The controller is further configured to hold the voltage applied to the control gate of the selected word line at the programming voltage over a second duration that is less than the first duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.