Wordline or pillar state detection for faster read access times
US12205653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2022 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jul 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.