Wafer-level design and wiring pattern for a semiconductor package
US12205904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2019 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | May 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.