Semiconductor package with intermetallic-compound solder-joint comprising solder, UBM, and reducing layer materials
US12206056B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Jan 21, 2025 |
| Priority date | — |
| Expiry date | Jun 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.