Semiconductor wafer testing system and related method for improving external magnetic field wafer testing
US12210055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jun 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.