Patent · US Active

Wafer-level test method for optoelectronic chips

US12210057B2 · kind B2 · utility

0Cited by

3References

11Claims

0Family size

Assignee

Jenoptik Optical Systems GmbH · DE

Inventors

Christian KARRAS · Jena, DE
Tobias Gnausch · Östringen, DE
Robert BUETTNER · Jena, DE
Kay Reetz · Weimar, DE
Armin Grundmann · Jena, DE
Thomas Kaden · Dresden, DE

Key dates

Filing date	Apr 12, 2022
Grant date	Jan 28, 2025
Priority date	—
Expiry date	Apr 12, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/311
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method for testing optoelectronic chips that are arranged on a wafer and comprise electric interfaces in the form of contact pads and optical interfaces, which are arranged in a fixed manner relative to the electric interfaces, in the form of optical deflecting elements, e.g. grating couplers, at a specified coupling angle. In the process, the wafer is adjusted in three adjustment steps in such a manner that one of the chips is positioned relative to a contacting module such that the electric interfaces of the chip and the contacting module are in contact with one another and the optical interfaces of the chip and the contacting module assume a maximum position of the optical coupling.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.