Semiconductor package including a dummy pattern
US12211777B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Jul 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.