Power semiconductor package having first and second lead frames

US12211824B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ivan Nikitin · Regensburg, DE
• Thorsten Scharf · Regensburg, DE
• Marco Bäßler · Oeversee, DE
• Andreas Grassmann · Villach, AT
• Waldemar Jakobi · Karlsruhe, DE

Key dates

• Filing date: Apr 5, 2023
• Grant date: Jan 28, 2025
• Expiry date: May 7, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H02M7/003
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.