Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
US12212327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2023 |
| Grant date | Jan 28, 2025 |
| Priority date | — |
| Expiry date | Feb 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1077
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.