Systems and methods for parallel testing of multiple namespaces located in a plurality of devices under test
US12216559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Jul 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.