Semiconductor device incorporating a substrate recess
US12218202B2 · kind B2 · utility
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75References
13Claims
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Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Feb 4, 2025 |
| Priority date | — |
| Expiry date | Mar 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.