Methods and apparatus for providing mask register optimization for vector operations
US12223324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Oct 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.