Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors
US12224344B2 · kind B2 · utility
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2References
14Claims
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Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Jun 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.