Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
US12224350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Sep 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.